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XR21V1414
4-CH FULL-SPEED USB UART
JUNE 2009 REV. 1.0.0
GENERAL DESCRIPTION
The XR21V1414 (V1414) is an enhanced 4-channel USB Universal Asynchronous Receiver and Transmitter (UART). The USB interface is fully compliant to Full Speed USB 2.0 specification that supports 12 Mbps USB data transfer rate. The USB interface also supports USB suspend, resume and remote wakeup operations. The V1414 operates from an internal 48MHz clock therefore no external crystal/oscillator is required like previous generation UARTs. With the fractional baud rate generator, any baud rate can accurately be generated using the internal 48MHz clock. The large 128-byte FIFO and 384-byte RX FIFO of the V1414 helps to optimize the overall data throughput for various applications. The Automatic Transceiver Direction control feature simplifies both the hardware and software for half-duplex RS-485 applications. If required, the multidrop (9-bit) mode with automatic half-duplex transceiver control feature further simplifies typical multidrop RS-485 applications. The V1414 operates from a single 2.97 to 3.63 volt power supply and has 5V tolerant inputs. The V1414 is available in a 48-pin TQFP package. Software drivers for Windows 2000, XP, Vista, and CE, as well as Linux and Mac are supported for the XR21V1414. APPLICATIONS
FEATURES
* USB 2.0 Compliant Interface

Supports 12 Mbps USB full-speed data rate Supports USB suspend, resume and remote wakeup operations Data rates up to 12 Mbps Fractional Baud Rate Generator 128 byte TX FIFO 384 byte RX FIFO 7, 8 or 9 data bits, 1 or 2 stop bits Automatic Hardware (RTS/CTS or DTR/DSR) Flow Control Automatic Software (Xon/Xoff) Flow Control Multidrop mode w/ Transceiver Control Half-Duplex mode Sleep Mode with Remote Wake-up Selectable GPIO or Modem I/O Auto Half-Duplex
* Enhanced Features of each UART

Multidrop mode w/ Auto TX Enable
* Internal 48 MHz clock * Single 2.97-3.63V power supply * 5V tolerant inputs * 48-pin TQFP package * Virtual COM Port drivers

* Portable Appliances * External Converters (dongles) * Battery-Operated Devices * Cellular Data Devices * Factory Automation and Process Controls * Industrial applications
Windows 2000, XP and Vista Windows CE 4.2, 5.0, 6.0 Linux Mac
Exar Corporation 48720 Kato Road, Fremont CA, 94538 * (510) 668-7000 * FAX (510) 668-7017 * www.exar.com
XR21V1414
4-CH FULL-SPEED USB UART FIGURE 1. XR21V1414 BLOCK DIAGRAM
REV. 1.0.0
3.3V VCC GND
Fractional BRG
128-byte TX FIFO 384-byte RX FIFO
TXA RXA GPIOA5/RTSA# GPIOA4/CTSA# GPIOA3/DTRA# GPIOA2/DSRA# GPIOA1/CDA# GPIOA0/RIA#
Internal Status and Control Registers USBD+ USBDUSB Slave Interface
GPIOs/ Modem IO
UART Channel A TXB RXB GPIOB[5:0]/ModemIO
UART Channel B (Same as Ch A) SDA SCL I2C Interface
UART Channel C (Same as Ch A)
TXC RXC GPIOC[5:0]/ModemIO TXD RXD GPIOD[5:0]/ModemIO
Internal 48MHz Oscillator
UART Channel D (Same as Ch A)
2
XR21V1414
REV. 1.0.0
4-CH FULL-SPEED USB UART
FIGURE 2. PIN OUT ASSIGNMENT
GPIOD0/RID# TXD RXD GND GND USBDUSBD+ VCC VCC GPIOD5/RTSD# GPIOD4/CTSD# GPIOD3/DTRD#
36 35 34 33 32 31 30 29 28 27 26 25 24 37 38 39 40 41 42 43 44 45 46 47 48 12 3 4 5 6 7 8 23 22 21 20 19 18 17 16 15 14 13 9 10 11 12
SCL SDA GPIOD1/CDD# VCC GND RXA TXA GPIOC0/RIC# GPIOC1/CDC# GPIOC2/DSRC# GPIOC3/DTRC# GPIOC4/CTSC#
XR21V1414 48-TQFP
GPIOC5/RTSC# RXC TXC GPIOA0/RIA# GPIOA1/CDA# GND VCC GPIOA2/DSRA# GPIOA3/DTRA# GPIOB0/RIB# GPIOB1/CDB# GPIOB2/DSRB#
ORDERING INFORMATION
PART NUMBER XR21V1414IM48 PACKAGE 48-pin TQFP OPERATING TEMPERATURE RANGE -40C to +85C DEVICE STATUS Active
GND LOWPOWER GPIOD2/DSRD# GND VCC GPIOA5/RTSA# GPIOA4/CTSA# TXB RXB GPIOB5/RTSB# GPIOB4/CTSB# GPIOB3/DTRB#
3
XR21V1414
4-CH FULL-SPEED USB UART
REV. 1.0.0
PIN DESCRIPTIONS
Pin Description
NAME 48-QFN PIN # TYPE DESCRIPTION
UART Channel A Signals RXA 31 I UART Channel A Receive Data or IR Receive Data. This pin has an internal pull-up resistor. Internal pull-up resistor is not disabled during suspend mode. UART Channel A Transmit Data or IR Transmit Data. General purpose I/O or UART Ring-Indicator input (active low). This pin has an internal pull-up resistor. Internal pull-up resistor is disabled during suspend mode. If using this GPIO as an input, a pull-up resistor is required to minimize the power consumption in the suspend mode. General purpose I/O or UART Carrier-Detect input (active low). This pin has an internal pull-up resistor. Internal pull-up resistor is disabled during suspend mode. If using this GPIO as an input, a pull-up resistor is required to minimize the power consumption in the suspend mode. General purpose I/O or UART Data-Set-Ready input (active low). This pin has an internal pull-up resistor. Internal pull-up resistor is disabled during suspend mode. If using this GPIO as an input, a pull-up resistor is required to minimize the power consumption in the suspend mode. General purpose I/O or UART Data-Terminal-Ready output (active low). This pin has an internal pull-up resistor. Internal pull-up resistor is disabled during suspend mode. If using this GPIO as an input, a pull-up resistor is required to minimize the power consumption in the suspend mode. General purpose I/O or UART Clear-to-Send input (active low). This pin has an internal pull-up resistor. Internal pull-up resistor is disabled during suspend mode. If using this GPIO as an input, a pull-up resistor is required to minimize the power consumption in the suspend mode. General purpose I/O or UART Request-to-Send output (active low). This pin has an internal pull-up resistor. Internal pull-up resistor is disabled during suspend mode. If using this GPIO as an input, a pull-up resistor is required to minimize the power consumption in the suspend mode.
TXA GPIOA0/RIA#
30 21
O I/O
GPIOA1/CDA#
20
I/O
GPIOA2/DSRA#
17
I/O
GPIOA3/DTRA#
16
I/O
GPIOA4/CTSA#
7
I/O
GPIOA5/RTSA#
6
I/O
UART Channel B Signals RXB 9 I UART Channel B Receive Data or IR Receive Data. This pin has an internal pull-up resistor. Internal pull-up resistor is not disabled during suspend mode. UART Channel B Transmit Data or IR Transmit Data. General purpose I/O or UART Ring-Indicator input (active low). This pin has an internal pull-up resistor. Internal pull-up resistor is disabled during suspend mode. If using this GPIO as an input, a pull-up resistor is required to minimize the power consumption in the suspend mode. General purpose I/O or UART Carrier-Detect input (active low). This pin has an internal pull-up resistor. Internal pull-up resistor is disabled during suspend mode. If using this GPIO as an input, a pull-up resistor is required to minimize the power consumption in the suspend mode.
TXB GPIOB0/RIB#
8 15
O I/O
GPIOB1/CDB#
14
I/O
4
XR21V1414
REV. 1.0.0
4-CH FULL-SPEED USB UART
Pin Description
NAME GPIOB2/DSRB# 48-QFN PIN # 13 TYPE I/O DESCRIPTION General purpose I/O or UART Data-Set-Ready input (active low). This pin has an internal pull-up resistor. Internal pull-up resistor is disabled during suspend mode. If using this GPIO as an input, a pull-up resistor is required to minimize the power consumption in the suspend mode. General purpose I/O or UART Data-Terminal-Ready output (active low). This pin has an internal pull-up resistor. Internal pull-up resistor is disabled during suspend mode. If using this GPIO as an input, a pull-up resistor is required to minimize the power consumption in the suspend mode. General purpose I/O or UART Clear-to-Send input (active low). This pin has an internal pull-up resistor. Internal pull-up resistor is disabled during suspend mode. If using this GPIO as an input, a pull-up resistor is required to minimize the power consumption in the suspend mode. General purpose I/O or UART Request-to-Send output (active low). This pin has an internal pull-up resistor. Internal pull-up resistor is disabled during suspend mode. If using this GPIO as an input, a pull-up resistor is required to minimize the power consumption in the suspend mode.
GPIOB3/DTRB#
12
I/O
GPIOB4/CTSB#
11
I/O
GPIOB5/RTSB#
10
I/O
UART Channel C Signals RXC 23 I UART Channel C Receive Data or IR Receive Data. This pin has an internal pull-up resistor. Internal pull-up resistor is not disabled during suspend mode. UART Channel C Transmit Data or IR Transmit Data. General purpose I/O or UART Ring-Indicator input (active low). This pin has an internal pull-up resistor. Internal pull-up resistor is disabled during suspend mode. If using this GPIO as an input, a pull-up resistor is required to minimize the power consumption in the suspend mode. General purpose I/O or UART Carrier-Detect input (active low). This pin has an internal pull-up resistor. Internal pull-up resistor is disabled during suspend mode. If using this GPIO as an input, a pull-up resistor is required to minimize the power consumption in the suspend mode. General purpose I/O or UART Data-Set-Ready input (active low). This pin has an internal pull-up resistor. Internal pull-up resistor is disabled during suspend mode. If using this GPIO as an input, a pull-up resistor is required to minimize the power consumption in the suspend mode. General purpose I/O or UART Data-Terminal-Ready output (active low). This pin has an internal pull-up resistor. Internal pull-up resistor is disabled during suspend mode. If using this GPIO as an input, a pull-up resistor is required to minimize the power consumption in the suspend mode. General purpose I/O or UART Clear-to-Send input (active low). This pin has an internal pull-up resistor. Internal pull-up resistor is disabled during suspend mode. If using this GPIO as an input, a pull-up resistor is required to minimize the power consumption in the suspend mode. General purpose I/O or UART Request-to-Send output (active low). This pin has an internal pull-up resistor. Internal pull-up resistor is disabled during suspend mode. If using this GPIO as an input, a pull-up resistor is required to minimize the power consumption in the suspend mode.
TXC GPIOC0/RIC#
22 29
O I/O
GPIOC1/CDC#
28
I/O
GPIOC2/DSRC#
27
I/O
GPIOC3/DTRC#
26
I/O
GPIOC4/CTSC#
25
I/O
GPIOC5/RTSC#
24
I/O
5
XR21V1414
4-CH FULL-SPEED USB UART Pin Description
NAME 48-QFN PIN # TYPE DESCRIPTION
REV. 1.0.0
UART Channel D Signals RXD 39 I UART Channel D Receive Data or IR Receive Data. This pin has an internal pull-up resistor. Internal pull-up resistor is not disabled during suspend mode. UART Channel D Transmit Data or IR Transmit Data. General purpose I/O or UART Ring-Indicator input (active low). This pin has an internal pull-up resistor. Internal pull-up resistor is disabled during suspend mode. If using this GPIO as an input, a pull-up resistor is required to minimize the power consumption in the suspend mode. General purpose I/O or UART Carrier-Detect input (active low). This pin has an internal pull-up resistor. Internal pull-up resistor is disabled during suspend mode. If using this GPIO as an input, a pull-up resistor is required to minimize the power consumption in the suspend mode. General purpose I/O or UART Data-Set-Ready input (active low). This pin has an internal pull-up resistor. Internal pull-up resistor is disabled during suspend mode. If using this GPIO as an input, a pull-up resistor is required to minimize the power consumption in the suspend mode. General purpose I/O or UART Data-Terminal-Ready output (active low). This pin has an internal pull-up resistor. Internal pull-up resistor is disabled during suspend mode. If using this GPIO as an input, a pull-up resistor is required to minimize the power consumption in the suspend mode. General purpose I/O or UART Clear-to-Send input (active low). This pin has an internal pull-up resistor. Internal pull-up resistor is disabled during suspend mode. If using this GPIO as an input, a pull-up resistor is required to minimize the power consumption in the suspend mode. General purpose I/O or UART Request-to-Send output (active low). This pin has an internal pull-up resistor. Internal pull-up resistor is disabled during suspend mode. If using this GPIO as an input, a pull-up resistor is required to minimize the power consumption in the suspend mode.
TXD GPIOD0/RID#
38 37
O I/O
GPIOD1/CDD#
34
I/O
GPIOD2/DSRD#
3
I/O
GPIOD3/DTRD#
48
I/O
GPIOD4/CTSD#
47
I/O
GPIOD5/RTSD#
46
I/O
USB Interface Signals USBD+ USBDI2C Interface Signals SDA 35 OD I2C-controller data input/output (open-drain). 1K pull-up resistor is required if an EEPROM is connected. An optional external I2C EEPROM can be used to store default configurations upon power-up including the USB Vendor ID and Device ID. If an EEPROM is not used, this pin can be used with the SCL pin to select the Remote Wake-up and Power modes. An external pull-up or pull-down resistor is required. See Table 1. 43 42 I/O I/O USB port differential data plus. This pin has a 1.5 K Ohm internal pull-up resistor. USB port differential data minus.
6
XR21V1414
REV. 1.0.0
4-CH FULL-SPEED USB UART
Pin Description
NAME SCL 48-QFN PIN # 36 TYPE I DESCRIPTION I2C-controller serial input clock. 1K pull-up resistor is required if an EEPROM is connected. An optional external I2C EEPROM can be used to store default configurations upon power-up including the USB Vendor ID and Device ID. If an EEPROM is not used, this pin can be used with the SDA pin to select the Remote Wake-up and Power modes. An external pull-up or pull-down resistor is required. See Table 1.
Ancillary Signals LOWPOWER 2 O Low power status output. This pin is HIGH when the XR21V1414 is in the suspend mode. This pin is LOW when the XR21V1414 is not in the suspend mode. An external pull-up or pull-down resistor is required on this pin. This pin is sampled upon power-on to configure the polarity of the LOWPOWER output during suspend mode. An external pull-up resistor will cause the LOWPOWER pin to be HIGH during suspend mode. An external pull-down resistor will cause the LOWPOWER pin to be LOW during suspend mode. +3.3V power supply. All inputs are 5V tolerant. Power supply common, ground.
VCC GND
5, 18, 33, 44, 45 1, 4, 19, 32, 40, 41
Pwr Pwr
NOTE: Pin type: I=Input, O=Output, I/O= Input/output, OD=Output Open Drain.
7
XR21V1414
4-CH FULL-SPEED USB UART 1.0 FUNCTIONAL DESCRIPTIONS 1.1 USB interface The USB interface of the V1414 is compliant with the USB 2.0 Full-Speed Specifications. The USB configuration model presented by the V1414 to the device driver is compatible to the Abstract Control Model of the USB Communication Device Class (CDC-ACM). The V1414 uses the following set of parameters:
REV. 1.0.0
* 1 Control Endpoint
Endpoint 0 as outlined in the USB specifications
* 1 Configuration is supported * 2 interfaces per UART channel

Each UART channel has a single interrupt endpoint Each UART channel have bulk-in and bulk-out endpoints USB Vendor ID
1.1.1
Exar's USB Vendor ID is 0x04E2. This is the default Vendor ID that is used for the V1414 unless a valid EEPROM is present on the I2C interface signals. If a valid EEPROM is present, the Vendor ID from the EEPROM will be used. 1.1.2 USB Product ID The default USB Product ID for the V1414 is 0x1414. If a valid EEPROM is present, the Product ID from the EEPROM will be used. 1.2 I2C Interface The I2C interface provides connectivity to an external I2C memory device (i.e. EEPROM) that can be read by the V1414 for configuration. The SDA and SCL are used to specify whether Remote Wakeup and/or Bus Powered configurations are to be supported. These pins are sampled at power-up. The following table describes how Remote Wakeup and Bus Powered support. TABLE 1: REMOTE WAKEUP AND POWER MODES
SDA 1 1 0 0 SCL 1 0 1 0 REMOTE WAKE-UP SUPPORT No No Yes Yes POWER MODE Self-Powered Bus-Powered Self-Powered Bus-Powered COMMENTS Default, if no EEPROM is present
8
XR21V1414
REV. 1.0.0
4-CH FULL-SPEED USB UART EEPROM Contents
1.2.1
The I2C address should be 0xA0. An EEPROM can be used to override default Vendor IDs and Device IDs, as well as other attributes and maximum power consumption. The EEPROM must contain 8 bytes of data as specified in Table 2 TABLE 2: EEPROM CONTENTS
EEPROM ADDRESS 0 1 2 3 4 5 6 7 CONTENTS Vendor ID (LSB) Vendor ID (MSB) Product ID (LSB) Product ID (MSB) Device Attributes Device Maximum Power Reserved Signature of 0x58 ('X'). If the signature is not correct, the contents of the EEPROM are ignored.
These values are uploaded from the EEPROM to the corresponding USB Standard Device Descriptor or Standard Configuration Descriptor. For details of the USB Descriptors, refer to the USB 2.0 specifications. 1.2.1.1 1.2.1.2 1.2.1.3 1.2.1.4 Vendor ID Product ID Device Attributes Device Maximum Power The Vendor ID value replaces the idVendor field in the USB Standard Device Descriptor. The Product ID value replaces the idProduct field in the USB Standard Device Descriptor. The Device Attributes value replaces the bmAttributes field in the USB Standard Configuration Descriptor. The Device Maximum Power value replaces the bMaxPower field in the USB Standard Configuration Descriptor. 1.3 UART Manager The UART Manager enables/disables each UART including the TX and RX FIFOs for each UART. The UART Manager is located in a separate register block from the 4 UART channels. 1.4 UART There are 4 enhanced UART channels in the V1414. Each UART channel is independent, therefore, they will need to be initialized and configured independently. Each UART can be configured via USB control transfers from the USB host. 1.4.1 Transmitter The transmitter consists of a 128-byte TX FIFO and a Transmit Shift Register (TSR). Once a bulk-out packet has been received and the CRC has been validated, the data bytes in that packet are written into the TX FIFO of the specified UART channel. Data from the TX FIFO is transferred to the TSR when the TSR is idle or has completed sending the previous data byte. The TSR shifts the data out onto the TX output pin at the data rate defined by the CLOCK_DIVISOR and TX_CLOCK_MASK registers. The transmitter sends the start bit followed by the data bits (starting with the LSB), inserts the proper parity-bit if enabled, and adds the stopbit(s). The transmitter can be configured for 7 or 8 data bits with parity or 9 data bits with no parity.
9
XR21V1414
4-CH FULL-SPEED USB UART 1.4.1.1 9-Bit Data Mode
REV. 1.0.0
In 9-bit data mode, two bytes of data must be written. The first byte that is loaded into the TX FIFO are the first 8 bits (data bits 7-0) of the 9-bit data. Bit-0 of the second byte that is loaded into the TX FIFO is bit-8 of the 9bit data. The data that is transmitted on the TX pin is as follows: start bit, 9-bit data, stop bit. 1.4.2 Receiver The receiver consists of a 384-byte RX FIFO and a Receive Shift Register (RSR). Data that is received in the RSR via the RX pin is transferred into the RX FIFO along with any error tags such as Framing, Parity, Break and Overrun errors. Data from the RX FIFO can be sent to the USB host by sending a bulk-in packet. 1.4.2.1 1.4.2.2 Character Mode Character + Status Mode In character mode, up to 64 bytes of data can be sent at a time to the USB host. In this mode, each 8-bit character and the 4 error bits associated with it can be transmitted to the USB host. The 4 error bits will be in the second byte following the 8-bit character. In this mode, up to 32 character bytes are sent per bulk-in packet. 1.4.2.3 9-Bit Data Mode In 9-bit data mode, two bytes of data are sent to the USB host for each byte 9-bit data that is received. The first byte sent to the USB host is the first 8-bits of data. Bit-0 of the second byte is the bit-9 of the data. 1.4.3 GPIO Each UART has 6 GPIOs. By default, the GPIOs are general purpose I/Os. However, there are few modes that can be enabled to add additional feature such as Auto RTS/CTS Flow control, Auto DTR/DSR Flow Control or Transceiver Enable Control. See Table 13. 1.4.4 Automatic RTS/CTS Hardware Flow Control GPIO5 and GPIO4 of the UART channel can be enabled as the RTS# and CTS# signals for Auto RTS/CTS flow control when GPIO_MODE[2:0] = '001' and FLOW_CONTROL[2:0] = '001'. Automatic RTS flow control is used to prevent data overrun errors in local RX FIFO by de-asserting the RTS signal to the remote UART. When there is room in the RX FIFO, the RTS pin will be re-asserted. Automatic CTS flow control is used to prevent data overrun to the remote RX FIFO. The CTS# input is monitored to suspend/restart the local transmitter (see Figure 3):
10
XR21V1414
REV. 1.0.0
4-CH FULL-SPEED USB UART
FIGURE 3. AUTO RTS AND CTS FLOW CONTROL OPERATION
Local UART UARTA Receiver FIFO Trigger Reached Auto RTS Trigger Level Transmitter Auto CTS Monitor RXA TXB Remote UART UARTB Transmitter Auto CTS Monitor Receiver FIFO Trigger Reached Auto RTS Trigger Level
RTSA# TXA
CTSB# RXB
CTSA# Assert RTS# to Begin Transmission 1 ON 2 7 ON 3 8 OFF
RTSB#
RTSA# CTSB# TXB
OFF
10 11
ON ON
Data Starts 4 RXA FIFO INTA (RXA FIFO Interrupt) Receive Data RX FIFO Trigger Level 5
6
Suspend
Restart 9
RTS High Threshold
RTS Low Threshold
12
RX FIFO Trigger Level
RTSCTS1
11
XR21V1414
4-CH FULL-SPEED USB UART 1.4.5 Automatic DTR/DSR Hardware Flow Control
REV. 1.0.0
Auto DTR/DSR hardware flow control behaves the same as the Auto RTS/CTS hardware flow control described above except that it uses the DTR# and DSR# signals. For Auto hardware flow control, FLOW_CONTROL[2:0] = '001'. GPIO3 and GPIO2 become DTR# and DSR#, respectively, when GPIO_MODE[2:0] = '010'. 1.4.6 Automatic XON/XOFF Software Flow Control When software flow control is enabled, the V1414 compares the receive data characters with the programmed Xon or Xoff characters. If the received character matches the programmed Xoff character, the V1414 will halt transmission as soon as the current character has completed transmission. Data transmission is resumed when a received character matches the Xon character. Software flow control is enabled when FLOW_CONTROL[2:0] = '010'. 1.4.7 Multidrop Mode with Automatic Half-Duplex Transceiver Control Multidrop mode with Automatic Half-Duplex Transceiver Control is enabled when GPIO_MODE[2:0] = '011' and FLOW_CONTROL[2:0] = '011'. 1.4.7.1 Receiver In this mode, the UART Receiver will automatically be enabled when an address byte (9th bit or parity bit is '1') is received that matches the value stored in the XON_CHAR or XOFF_CHAR register. The address byte will not be loaded into the RX FIFO. All subsequent data bytes will be loaded into the RX FIFO. The UART Receiver will automatically be disabled when an address byte is received that does not match the values in the XON_CHAR or XOFF_CHAR register. 1.4.7.2 Transmitter GPIO5/RTS# pin behaves as control pin for the direction of a half-duplex RS-485 transceiver. The polarity of the GPIO5/RTS# pin can be configured via GPIO_MODE[3]. When the UART is not transmitting data, the GPIO5/RTS# pin will be de-asserted. The GPIO5/RTS# pin will be asserted immediately before the UART starts transmitting data. When the UART is done transmitting data, the GPIO5/RTS# pin will be de-asserted. 1.4.8 Multidrop Mode with Automatic Transmitter Enable Multidrop mode with Automatic Transmitter Enable is enabled when GPIO_MODE[2:0] = '100' and FLOW_CONTROL[2:0] = '100'. 1.4.8.1 1.4.8.2 Receiver Transmitter The behavior of the receiver is the same in this mode as it is in the Address Match mode described above. When there is an address match with the XON_CHAR register, the GPIO5/RTS# pin is asserted and remains asserted whether the UART is transmitting data or not. The GPIO5/RTS# pin will be de-asserted when an address byte is received that does not match the value in the XON_CHAR register. The polarity of the GPIO5/ RTS# pin can be configured via GPIO_MODE[3]. 1.4.9 Programmable Turn-Around Delay By default, the GPIO5/RTS# pin will be de-asserted immediately after the stop bit of the last byte has been shifted. However, this may not be ideal for systems where the signal needs to propagate over long cables. Therefore, the de-assertion of GPIO5/RTS# pin can be delayed from 1 to 15 bit times via the XCVR_EN_DELAY register to allow for the data to reach distant UARTs. 1.4.10 Half-Duplex Mode Half-duplex mode is enabled when FLOW_CONTROL[3] = 1. In this mode, the UART will ignore any data on the RX input when the UART is transmitting data.
12
XR21V1414
REV. 1.0.0
4-CH FULL-SPEED USB UART
2.0 USB CONTROL COMMANDS The following table shows all of the USB Control Commands that are supported by the V1414. Commands included are standard USB commands, CDC-ACM commands and custom Exar commands. . TABLE 3: SUPPORTED USB CONTROL COMMANDS
NAME DEV GET_STATUS IF GET_STATUS REQUEST TYPE 0x80 0x81 REQUEST 0 0 VALUE 0 0 0 0 0 1-4, 129132 0-4, 129136 0 0-4, 129136 0 0 0-4, 129136 0 0 0 0 0 0-7 0, 2, 4, 6 0, 2, 4, 6 0, 2, 4, 6 INDEX 0 0 LENGTH 2 2 0 0 Interface: zero DESCRIPTION Device: remote wake-up + self-powered
EP GET_STATUS
0x82
0
0
0
0
2
0 Endpoint: halted
DEV CLEAR_FEATURE EP CLEAR_FEATURE
0x00 0x02
1 1
1 0
0 0
0 0
0 0
0 0
Device remote wake-up
Endpoint halt
DEV SET_FEATURE DEV SET_FEATURE EP SET_FEATURE
0x00 0x00 0x02
3 3 3
1 2 0
00 0 0
0 test 0
0 0 0
0 0 0
Device remote wake-up Test mode
Endpoint halt
SET_ADDRESS GET_DESCRIPTOR GET_DESCRIPTOR GET_CONFIGURATION SET_CONFIGURATION GET_INTERFACE CDC_ACM_IF SET_LINE_CODING CDC_ACM_IF GET_LINE_CODING CDC_ACM_IF SET_CONTROL_LINE_STATE
0x00 0x80 0x80 0x80 0x00 0x81 0x21 0xA1 0x21
5 6 6 8 9 10 32 33 34
addr 0 0 0 n 0 0 0 val
0 1 2 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
0 len LSB len LSB 1 0 1 7 7 0
0 len MSB len MSB 0 0 0 0 0 0 Set the UART baud rate, parity, stop bits, etc. Get the UART baud rate, parity, stop bits, etc. Set UART control lines Device descriptor Configuration descriptor
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XR21V1414
4-CH FULL-SPEED USB UART TABLE 3: SUPPORTED USB CONTROL COMMANDS
NAME CDC_ACM_IF SEND_BREAK XR_SET_REG REQUEST TYPE 0x21 0x40 REQUEST 35 0 VALUE val LSB val val MSB 0 INDEX 0, 2, 4, 6 0 LENGTH 0 0 0 0 DESCRIPTION Send a break for the specified duration Exar custom command: set one 8-bit register val: 8-bit register value register address: see
REV. 1.0.0
regis- block ter
Table 6 on page 16
block number: see Table 4
on page 14
XR_GETN_REG 0xC0 1 0 0 regis- block count count LSB MSB ter Exar custom register: get count 8-bit registers register address: see
Table 6 on page 16 block number: see Table 4 on page 14
2.1
UART Block Numbers
The table below lists the block numbers for accessing each of the UART channels and the UART Manager.. TABLE 4: CONTROL BLOCKS
BLOCK NAME UART Channel A UART Channel B UART Channel C UART Channel D UART Manager BLOCK NUMBER 0 1 2 3 4 DESCRIPTION The configuration and control registers for UART channel A. The configuration and control registers for UART channel B. The configuration and control registers for UART channel C. The configuration and control registers for UART channel D. The control registers for the UART Manager. The UART Manager enables/disables the TX and RX FIFOs for each UART.
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XR21V1414
REV. 1.0.0
4-CH FULL-SPEED USB UART
3.0 REGISTER SET DESCRIPTION The internal register set of the V1414 consists of 2 different types of registers: UART Manager and UART registers. The UART Manager controls the TX, RX and FIFOs of all UART channels. The UART registers configure and control the remaining UART channel functionality not related to the UART FIFO. 3.1 UART Manager Registers.. TABLE 5: UART MANAGER REGISTERS
ADDRESS 0X10 0X11 0X12 0x13 0X18 0X19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F REGISTER NAME FIFO_ENABLE_CHA FIFO_ENABLE_CHB FIFO_ENABLE_CHC FIFO_ENABLE_CHD RX_FIFO_RESET_CHA RX_FIFO_RESET_CHB RX_FIFO_RESET_CHC RX_FIFO_RESET_CHD TX_FIFO_RESET_CHA TX_FIFO_RESET_CHB TX_FIFO_RESET_CHC TX_FIFO_RESET_CHD BIT-7 0 0 0 0 Bit-7 Bit-7 Bit-7 Bit-7 Bit-7 Bit-7 Bit-7 Bit-7 BIT-6 0 0 0 0 Bit-6 Bit-6 Bit-6 Bit-6 Bit-6 Bit-6 Bit-6 Bit-6 BIT-5 0 0 0 0 Bit-5 Bit-5 Bit-5 Bit-5 Bit-5 Bit-5 Bit-5 Bit-5 BIT-4 0 0 0 0 Bit-4 Bit-4 Bit-4 Bit-4 Bit-4 Bit-4 Bit-4 Bit-4 BIT-3 0 0 0 0 Bit-3 Bit-3 Bit-3 Bit-3 Bit-3 Bit-3 Bit-3 Bit-3 BIT-2 0 0 0 0 Bit-2 Bit-2 Bit-2 Bit-2 Bit-2 Bit-2 Bit-2 Bit-2 BIT-1 RX RX RX RX Bit-1 Bit-1 Bit-1 Bit-1 Bit-1 Bit-1 Bit-1 Bit-1 BIT-0 TX TX TX TX Bit-0 Bit-0 Bit-0 Bit-0 Bit-0 Bit-0 Bit-0 Bit-0
FIFO_ENABLE Registers Enables the RX FIFO and TX FIFOs. For proper functionality, the UART TX and RX must be enabled in the following order: FIFO_ENABLE_CHx = 0x1 UART_ENABLE = 0x3 FIFO_ENABLE_CHx = 0x3 // Enable TX FIFO // Enable TX and RX of that channel // Enable RX FIFO
RX_FIFO_RESET and TX_FIFO_RESET Registers Writing a non-zero value to these registers resets the FIFOs.
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XR21V1414
4-CH FULL-SPEED USB UART 3.2 UART Register Map TABLE 6: UART REGISTERS
ADDRESS 0X00 0X01 0X02 0X03 0X04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A REGISTER NAME Reserved Reserved Reserved UART_ENABLE CLOCK_DIVISOR0 CLOCK_DIVISOR1 CLOCK_DIVISOR2 TX_CLOCK_MASK0 TX_CLOCK_MASK1 RX_CLOCK_MASK0 RX_CLOCK_MASK1 CHARACTER_FORMAT FLOW_CONTROL Reserved Reserved Reserved XON_CHAR XOFF_CHAR Reserved ERROR_STATUS TX_BREAK XCVR_EN_DELAY Reserved Reserved Reserved Reserved GPIO_MODE 0 0x1B 0x1D 0x1E 0x1F GPIO_DIRECTION GPIO_SET GPIO_CLEAR GPIO_STATUS 0 0 0 0 0 0 0 0 0 0 GPIO5 GPIO5 GPIO5 GPIO5 0 GPIO4 GPIO4 GPIO4 GPIO4 BIT-7 0 0 0 0 Bit-7 Bit-15 0 Bit-7 Bit-15 Bit-7 Bit-15 Stop 0 0 0 0 Bit-7 Bit-7 0 Break Status Bit-7 0 0 0 0 0 0 0 0 0 Bit-6 Bit-6 0 Overrun Error Bit-6 0 0 0 0 0 BIT-6 0 0 0 0 Bit-6 Bit-14 0 Bit-6 Bit-14 Bit-6 Bit-14 BIT-5 0 0 0 0 Bit-5 Bit-13 0 Bit-5 Bit-13 Bit-5 Bit-13 Parity 0 0 0 0 Bit-5 Bit-5 0 Parity Error Bit-5 0 0 0 0 0 0 0 0 0 Bit-4 Bit-4 0 Framing Error Bit-4 0 0 0 0 0 0 0 0 0 XCVR Enable Polarity GPIO3 GPIO3 GPIO3 GPIO3 GPIO2 GPIO2 GPIO2 GPIO2 0 0 0 0 HalfDuplex 0 0 0 Bit-3 Bit-3 0 Break Error Bit-3 BIT-4 0 0 0 0 Bit-4 Bit-12 0 Bit-4 Bit-12 Bit-4 Bit-12 BIT-3 0 0 0 0 Bit-3 Bit-11 0 Bit-3 Bit-11 Bit-3 Bit-11 BIT-2 0 0 0 0 Bit-2 Bit-10 Bit-18 Bit-2 Bit-10 Bit-2 Bit-10 BIT-1 0 0 0 RX Bit-1 Bit-9 Bit-17 Bit-1 Bit-9 Bit-1 Bit-9 BIT-0 0 0 0 TX Bit-0 Bit-8 Bit-16 Bit-0 Bit-8 Bit-0 Bit-8
REV. 1.0.0
Data Bits Flow Control Mode Select 0 0 0 Bit-2 Bit-2 0 0 Bit-2 Delay 0 0 0 0 Mode Select GPIO1 GPIO1 GPIO1 GPIO1 GPIO0 GPIO0 GPIO0 GPIO0 0 0 0 0 0 0 0 Bit-1 Bit-1 0 0 Bit-1 0 0 0 Bit-0 Bit-0 0 0 Bit-0
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XR21V1414
REV. 1.0.0
4-CH FULL-SPEED USB UART UART_ENABLE Register Description (Read/Write)
3.3 3.3.1
UART Register Descriptions
This register enables the UART TX and RX. For proper functionality, the UART TX and RX must be enabled in the following order: FIFO_ENABLE_CHx = 0x1 UART_ENABLE = 0x3 FIFO_ENABLE_CHx = 0x3 UART_ENABLE[0]: Enable UART TX // Enable TX FIFO // Enable TX and RX of that channel // Enable RX FIFO
* Logic 0 = UART TX disabled. * Logic 1 = UART TX enabled.
UART_ENABLE[1]: Enable UART RX
* Logic 0 = UART RX disabled. * Logic 1 = UART RX enabled.
UART_ENABLE[7:2]: Reserved These bits are reserved and should remain '0'. 3.3.2 CLOCK_DIVISOR0, CLOCK_DIVISOR1, CLOCK_DIVISOR2 Register Description (Read/Write) These registers are used for programming the baud rate. The V1414 uses a 19-bit divisor and 16-bit mask register. Using the internal 48MHz oscillator, the 19-bit divisor is calculated as follows: CLOCK_DIVISOR = Trunc ( 48000000 / Baud Rate ) For example, if the the baud rate is 115200bps, then CLOCK_DIVISOR = Trunc ( 48000000 / 115200 ) = Trunc (416.66667) = 416 CLOCK_DIVISOR0[7:0]: Baud rate clock divisor bits [7:0] CLOCK_DIVISOR1[7:0]: Baud rate clock divisor bits [15:8] CLOCK_DIVISOR2[2:0]: Baud rate clock divisor bits [18:16] CLOCK_DIVISOR2[7:3]: Reserved These bits are reserved and should remain '0'. 3.3.3 TX_CLOCK_MASK0, TX_CLOCK_MASK1 Register Description (Read/Write) A look-up table is used for the value of the 16-bit TX Clock mask registers. The index of the look-up table is calculated as follows: index = Trunc ( ( ( 48000000 / Baud Rate ) - CLOCK_DIVISOR ) * 32) For example, if the baud rate is 115200bps, then the index will be: index = Trunc ( ( ( 48000000 / 115200 ) - 416 ) * 32) = Trunc (21.3333) = 21 The values for some baud rates to program the TX_CLOCK_MASK registers are listed in Table 7. For baud rates that are not listed, use the index to select TX_CLOCK_MASK register values from Table 8. 3.3.4 RX_CLOCK_MASK0, RX_CLOCK_MASK1 Register Description (Read/Write) The values for some baud rates to program the RX_CLOCK_MASK registers are listed in Table 7. For baud rates that are not listed, use the same index calculated for the TX_CLOCK_MASK register to select RX_CLOCK_MASK register values from Table 8.
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XR21V1414
4-CH FULL-SPEED USB UART TABLE 7: CLOCK DIVISOR AND CLOCK MASK VALUES FOR COMMON BAUD RATES
BAUD RATE (BPS) 1200 2400 4800 9600 19200 38400 57600 115200 230400 460800 500000 576000 921600 1000000 1152000 1500000 2000000 2500000 3000000 3125000 3500000 4000000 4250000 6250000 8000000 12000000 CLOCK DIVISOR (DECIMAL) 40000 20000 10000 5000 2500 1250 833 416 208 104 96 83 52 48 41 32 24 19 16 15 13 12 11 7 6 4 TX CLOCK MASK (HEX) 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0912 0x0B6D 0x0912 0x0208 0x0000 0x0912 0x0040 0x0000 0x0B6D 0x0000 0x0000 0x0104 0x0000 0x0492 0x076D 0x0000 0x0122 0x0B6D 0x0000 0x0000 RX CLOCK MASK (HEX) 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0924 0x0B6A 0x0924 0x0040 0x0000 0x0924 0x0000 0x0000 0x0DB6 0x0000 0x0000 0x0108 0x0000 0x0492 0x0BB6 0x0000 0x0224 0x0DB6 0x0000 0x0000
REV. 1.0.0
For baud rates that are not listed in the table above, use the index value calcuated using the formula in "Section 3.3.3, TX_CLOCK_MASK0, TX_CLOCK_MASK1 Register Description (Read/Write)" on page 17 to determine which TX Clock and RX Clock Mask register values to use from Table 8. For the the RX Clock Mask register, there are 2 values listed and would depend on whether the Clock Divisor is even or odd. For even Clock Divisors, use the value from the first column. For odd Clock Divisors, use the value from the last column.
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XR21V1414
REV. 1.0.0
4-CH FULL-SPEED USB UART
TABLE 8: TX AND RX CLOCK MASK VALUES
INDEX (DECIMAL) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 TX CLOCK MASK (HEX) 0x0000 0x0000 0x0100 0x0020 0x0010 0x0208 0x0104 0x0844 0x0444 0x0122 0x0912 0x0492 0x0252 0x094A 0x052A 0x0AAA 0x0AAA 0x0555 0x0B55 0x06B5 0x05B5 0x0B6D 0x076D 0x0EDD 0x0DDD 0x07BB 0x0F7B 0x0DF7 0x07F7 0x0FDF 0x0F7F 0x0FFF RX CLOCK MASK (HEX) EVEN CLOCK DIVISOR 0x0000 0x0000 0x0000 0x0400 0x0100 0x0040 0x0820 0x0210 0x0110 0x0888 0x0448 0x0248 0x0928 0x04A4 0x0AA4 0x0954 0x0554 0x0AD4 0x0AB4 0x05AC 0x0D6C 0x0B6A 0x06DA 0x0DDA 0x0BBA 0x0F7A 0x0EF6 0x0BF6 0x0FEE 0x0FBE 0x0EFE 0x0FFE RX CLOCK MASK (HEX) ODD CLOCK DIVISOR 0x0000 0x0000 0x0100 0x0020 0x0010 0x0208 0x0108 0x0884 0x0444 0x0224 0x0924 0x0492 0x0292 0x0A52 0x054A 0x04AA 0x0AAA 0x05AA 0x055A 0x0B56 0x06D6 0x0DB6 0x0BB6 0x076E 0x0EEE 0x0DDE 0x07DE 0x0F7E 0x0EFE 0x07FE 0x0FFE 0x0FFD
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XR21V1414
4-CH FULL-SPEED USB UART 3.3.5 CHARACTER_FORMAT Register Description (Read/Write)
REV. 1.0.0
This register controls the character format such as the word length (7, 8 or 9), parity (odd, even, forced '0', or forced '1') and number of stop bits (1 or 2). CHARACTER_FORMAT[3:0]: Data Bits. TABLE 9: DATA BITS
DATA BITS 7 8 9 CHARACTER_FORMAT[3:0] 0111 1000 1001
All other values for CHARACTER_FORMAT[3:0] are reserved. CHARACTER_FORMAT[6:4]: Parity Mode Select These bits select the parity mode. If 9-bit data mode has been selected, then writing to these bits will not have any effect. In other words, there will not be an additional parity bit. TABLE 10: PARITY SELECTION
BIT-6 0 0 0 0 1 BIT-5 0 0 1 1 0 BIT-4 0 1 0 1 0 PARITY SELECTION No parity Odd parity Even parity Force parity to mark, "1" Force parity to space, "0"
CHARACTER_FORMAT[7]: Stop Bit select This register selects the number of stop bits to add to the transmitted character and how many stop bits to check for in the received character. TABLE 11: STOP BIT SELECTION
BIT-7 0 1 NUMBER OF STOP BITS 1 stop bit 2 stop bits
3.3.6
FLOW_CONTROL Register Description (Read/Write)
These registers select the flow control mode. These registers should only be written to when the UART is disabled. Writing to the FLOW_CONTROL register when the UART is enabled will result in undefined behavior.
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XR21V1414
REV. 1.0.0
4-CH FULL-SPEED USB UART TABLE 12: FLOW CONTROL MODE SELECTION
FLOW_CONTROL[2:0]: Flow control mode select
BIT-2 0 0 0 0 1
BIT-1 0 0 1 1 0
BIT-0 0 1 0 1 0 No flow control. HW flow control enabled SW flow control enabled
MODE DESCRIPTION
Multidrop mode with Automatic Half-Duplex Transceiver control Multidrop mode with Automatic Transmitter Enable
FLOW_CONTROL[3]: Half-Duplex Mode
* Logic 0 = Normal (full-duplex) mode. The UART can transmit and receive data at the same time. * Logic 1 = Half-duplex Mode. In half-duplex mode, any data on the RX pin is ignored when the UART is
transmitting data. FLOW_CONTROL[7:4]: Reserved These bits are reserved and should remain '0'. 3.3.7 XON_CHAR, XOFF_CHAR Register Descriptions (Read/Write) The XON_CHAR and XOFF_CHAR registers store the XON and XOFF characters, respectively, that are used in the Automatic Software Flow control. XON_CHAR[7:0]: XON Character In Automatic Software Flow control mode, the UART will resume data transmission when the XON character has been received. For behavior in the Address Match mode, see "Section 1.4.7, Multidrop Mode with Automatic Half-Duplex Transceiver Control" on page 12. For behavior in the Address Match with TX Flow Control mode, see "Section 1.4.8, Multidrop Mode with Automatic Transmitter Enable" on page 12. XOFF_CHAR[7:0]: XOFF Character In Automatic Software Flow control mode, the UART will suspend data transmission when the XOFF character has been received. For behavior in the Address Match mode, see "Section 1.4.7, Multidrop Mode with Automatic Half-Duplex Transceiver Control" on page 12. For behavior in the Address Match with TX Flow Control mode, see "Section 1.4.8, Multidrop Mode with Automatic Transmitter Enable" on page 12. 3.3.8 ERROR_STATUS Register Description - Read-only This register reports any errors that may have occurred on the line such as break, framing, parity and overrun. ERROR_STATUS[2:0]: Reserved These bits are reserved. Any values read from these bits should be ignored. ERROR_STATUS[3]: Break error
* Logic 0 = No break condition * Logic 1 = A break condition has been detected (clears after read).
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XR21V1414
4-CH FULL-SPEED USB UART ERROR_STATUS[4]: Framing Error
REV. 1.0.0
* Logic 0 = No framing error * Logic 1 = A framing error has been detected (clears after read). A framing error occurs when a stop bit is not
present when it is expected. ERROR_STATUS[5]: Parity Error
* Logic 0 = No parity error * Logic 1 = A parity error has been detected (clears after read).
ERROR_STATUS[6]: Overrun Error
* Logic 0 = No overrun error * Logic 1 = An overrun error has been detected (clears after read). An overrun error occurs when the RX FIFO
is full and another byte of data is received. ERROR_STATUS[7]: Break Status
* Logic 0 = Break condition is no longer present. * Logic 1 = Break condition is currently being detected.
3.3.9 TX_BREAK Register Description (Read/Write) Writing a non-zero value to this register causes a break condition to be generated continuously until the register is cleared. If data is being shifted out of the TX pin, the data will be completed shifted out before the break condition is generated. 3.3.10 XCVR_EN_DELAY Register Description (Read/Write) XCVR_EN_DELAY[3:0]: Turn-around delay This is the number of bit times to wait before changing the direction of the transceiver from transmit to receive when half-duplex mode is enabled. XCVR_EN_DELAY[3:0]: Reserved These bits are reserved and should be '0'. 3.3.11 GPIO_MODE Register Description (Read/Write) GPIO_MODE[2:0]: GPIO Mode Select There are 4 modes of operation for the GPIOs. The descriptions can be found in "Section 1.4, UART" on page 9. TABLE 13: GPIO MODES
BITS [2:0] 000 001 010 011 100 GPIO0 GPIO0 GPIO0 GPIO0 GPIO0 GPIO0 GPIO1 GPIO1 GPIO1 GPIO1 GPIO1 GPIO1 GPIO2 GPIO2 GPIO2 DSR# GPIO2 GPIO2 GPIO3 GPIO3 GPIO3 DTR# GPIO3 GPIO3 GPIO4 GPIO4 CTS# GPIO4 GPIO4 GPIO4 GPIO5 GPIO5 RTS# GPIO5 XCVR Enable XCVR Enable GPIO Mode Auto RTS/CTS HW Flow Control Auto DTR/DSR HW Flow Control Multidrop Mode with Auto Half-Duplex Transceiver Control Multidrop Mode with Auto TX Enable MODE DESCRIPTION
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XR21V1414
REV. 1.0.0
4-CH FULL-SPEED USB UART
GPIO_MODE[3]: Transceiver Enable Polarity
* Logic 0 = Low for TX * Logic 1 = High for TX
GPIO_MODE[7:4]: Reserved These register bits are reserved. When writing to these bits, the value should be '0'. When reading from these bits, they are undefined and should be ignored. 3.3.12 GPIO_DIRECTION Register Description (Read/Write) This register controls the direction of the GPIO if it is not controlled by the GPIO_MODE register. GPIO_DIRECTION[5:0]: GPIOx Direction
* Logic 0 = GPIOx is an input. * Logic 1 = GPIOx is an output.
GPIO_DIRECTION[7:6]: Reserved These register bits are reserved and should be '0'. 3.3.13 GPIO_SET Register Description (Read/Write) Writing a '1' in this register drives the GPIO output high. Writing a '0' to a bit has no effect. Bits 7-6 are unused and should be '0'. 3.3.14 GPIO_CLEAR Register Description (Read/Write) Writing a '1' in this register drives the GPIO output low. Writing a '0' to a bit has no effect. Bits 7-6 are unused and should be '0'. 3.3.15 GPIO_STATUS Register Description (Read-Only) This register reports the current state of the GPIO pin.
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XR21V1414
4-CH FULL-SPEED USB UART 4.0 ELECTRICAL CHARACTERISTICS DC ELECTRICAL CHARACTERISTICS - POWER CONSUMPTION UNLESS OTHERWISE NOTED: TA = -40O TO +85OC, VCC IS 2.97 TO 3.63V
SYMBOL ICC ISusp PARAMETER MIN Power Supply Current Suspend mode Current LIMITS 3.3V TYP 16 2 UNITS MAX 20 2.15 mA mA CONDITIONS
REV. 1.0.0
DC ELECTRICAL CHARACTERISTICS - UART & GPIO PINS UNLESS OTHERWISE NOTED: TA = -40O TO +85OC, VCC IS 2.97 TO 3.63V
SYMBOL VIL VIH VOL VOH IIL IIH CIN PARAMETER MIN Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Input Low Leakage Current Input High Leakage Current Input Pin Capacitance 2.2 10 10 5 -0.3 2.0 LIMITS 3.3V MAX 0.8 5.5 0.3 V V V V uA uA pF IOL = 4 mA IOH = -4 mA UNITS CONDITIONS
DC ELECTRICAL CHARACTERISTICS - USB I/O PINS UNLESS OTHERWISE NOTED: TA = -40O TO +85OC, VCC IS 2.97 TO 3.63V
SYMBOL VIL VIH VOL VOH VDrvZ IOSC PARAMETER MIN Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Driver Output Impedance Open short current Current -0.3 2.0 0 2.8 28 LIMITS 3.3V MAX 0.8 5.5 0.3 3.6 44 35 V V V V Ohms mA 1.5 V on USBD+ and USBDExternal 15 K Ohm to GND on USBD- pin External 15 K Ohm to GND on USBD- pin UNITS CONDITIONS
24
XR21V1414
REV. 1.0.0
4-CH FULL-SPEED USB UART
PACKAGE DIMENSIONS (48 PIN TQFP - 7 X 7 X 1 mm)
D D1 36 25
37
24
D1
D
48
13
1 B A2 e
1 2
C A Seating Plane A1 L
Note: The control dimension is the millimeter column INCHES SYMBOL A A1 A2 B C D D1 e L a MIN 0.039 0.002 0.037 0.007 0.004 0.346 0.272 MAX 0.047 0.006 0.041 0.011 0.008 0.362 0.280 MILLIMETERS MIN 1.00 0.05 0.95 0.17 0.09 8.80 6.90 0.50 BSC 0.45 0x 0.75 7x MAX 1.20 0.15 1.05 0.27 0.20 9.20 7.10
0.020 BSC 0.018 0x 0.030 7x
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XR21V1414
4-CH FULL-SPEED USB UART REVISION HISTORY
DATE June 2009 REVISION 1.0.0 Final Datasheet. DESCRIPTION
REV. 1.0.0
NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user's specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 2009 EXAR Corporation Datasheet June 2009. Send your UART technical inquiry with technical details to hotline: uarttechsupport@exar.com. Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
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